VLSI Architecture of Pipelined Booth Wallace MAC Unit

This paper describes the pipelined architecture of high-speed modified Booth Wallace Multiply and Accumulator. The proposed multiply and accumulate circuits are based on the Booth algorithm and the pipelining techniques, which are most widely used to accelerate the multiplication speed. A 32-bit MAC Unit is designed in which the multiplication is done using the Modified Booth Wallace Multiplier and in the final stage addition of multiplier and in accumulator the Carry Select Adder is used and the pipelining is done in the Booth Multiplier and Wallace Tree. This MAC is described in VHDL and synthesized the circuit using 90 nm standard cell library on FPGA and Synopsys Design Compiler. This MAC has higher speed than conventional Booth Wallace MAC Unit.